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NXP Semiconductors /LPC43xx /RGU /RESET_ACTIVE_STATUS1

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Interpret as RESET_ACTIVE_STATUS1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIMER0_RST)TIMER0_RST 0 (TIMER1_RST)TIMER1_RST 0 (TIMER2_RST)TIMER2_RST 0 (TIMER3_RST)TIMER3_RST 0 (RITIMER_RST)RITIMER_RST 0 (SCT_RST)SCT_RST 0 (MOTOCONPWM_RST)MOTOCONPWM_RST 0 (QEI_RST)QEI_RST 0 (ADC0_RST)ADC0_RST 0 (ADC1_RST)ADC1_RST 0 (DAC_RST)DAC_RST 0 (RESERVED)RESERVED 0 (UART0_RST)UART0_RST 0 (UART1_RST)UART1_RST 0 (UART2_RST)UART2_RST 0 (UART3_RST)UART3_RST 0 (I2C0_RST)I2C0_RST 0 (I2C1_RST)I2C1_RST 0 (SSP0_RST)SSP0_RST 0 (SSP1_RST)SSP1_RST 0 (I2S_RST)I2S_RST 0 (SPIFI_RST)SPIFI_RST 0 (CAN1_RST)CAN1_RST 0 (CAN0_RST)CAN0_RST 0 (M0APP_RST)M0APP_RST 0 (SGPIO_RST)SGPIO_RST 0 (SPI_RST)SPI_RST 0 (RESERVED)RESERVED 0 (ADCHS_RST)ADCHS_RST 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED

Description

Reset active status register 1

Fields

TIMER0_RST

Current status of the TIMER0_RST 0 = Reset asserted 1 = No reset
TIMER1_RST

Current status of the TIMER1_RST 0 = Reset asserted 1 = No reset
TIMER2_RST

Current status of the TIMER2_RST 0 = Reset asserted 1 = No reset
TIMER3_RST

Current status of the TIMER3_RST 0 = Reset asserted 1 = No reset
RITIMER_RST

Current status of the RITIMER_RST 0 = Reset asserted 1 = No reset
SCT_RST

Current status of the SCT_RST 0 = Reset asserted 1 = No reset
MOTOCONPWM_RST

Current status of the MOTOCONPWM_RST 0 = Reset asserted 1 = No reset
QEI_RST

Current status of the QEI_RST 0 = Reset asserted 1 = No reset
ADC0_RST

Current status of the ADC0_RST 0 = Reset asserted 1 = No reset
ADC1_RST

Current status of the ADC1_RST 0 = Reset asserted 1 = No reset
DAC_RST

Current status of the DAC_RST 0 = Reset asserted 1 = No reset
RESERVED

Reserved.
UART0_RST

Current status of the UART0_RST 0 = Reset asserted 1 = No reset
UART1_RST

Current status of the UART1_RST 0 = Reset asserted 1 = No reset
UART2_RST

Current status of the UART2_RST 0 = Reset asserted 1 = No reset
UART3_RST

Current status of the UART3_RST 0 = Reset asserted 1 = No reset
I2C0_RST

Current status of the I2C0_RST 0 = Reset asserted 1 = No reset
I2C1_RST

Current status of the I2C1_RST 0 = Reset asserted 1 = No reset
SSP0_RST

Current status of the SSP0_RST 0 = Reset asserted 1 = No reset
SSP1_RST

Current status of the SSP1_RST 0 = Reset asserted 1 = No reset
I2S_RST

Current status of the I2S_RST 0 = Reset asserted 1 = No reset
SPIFI_RST

Current status of the SPIFI_RST 0 = Reset asserted 1 = No reset
CAN1_RST

Current status of the CAN1_RST 0 = Reset asserted 1 = No reset
CAN0_RST

Current status of the CAN0_RST 0 = Reset asserted 1 = No reset
M0APP_RST

Current status of the M0APP_RST 0 = Reset asserted 1 = No reset
SGPIO_RST

Current status of the SGPIO_RST 0 = Reset asserted 1 = No reset
SPI_RST

Current status of the SPI_RST 0 = Reset asserted 1 = No reset
RESERVED

Reserved.
ADCHS_RST

Current status of the ADCHS_RST 0 = Reset asserted 1 = No reset
RESERVED

Reserved.
RESERVED

Reserved.
RESERVED

Reserved.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data